By Yongquan Fan
High-Speed Serial Interface (HSSI) units became common in communications, from the embedded to high-performance computing platforms, and from on-chip to a large haul. trying out of HSSIs has been a tough subject as a result of sign integrity matters, lengthy try time and the necessity of pricy tools. Accelerating attempt, Validation and Debug of excessive pace Serial Interfaces offers leading edge try and debug ways and particular directions on easy methods to arrive to useful try of recent high-speed interfaces.
Accelerating try out, Validation and Debug of excessive pace Serial Interfaces first proposes a brand new set of rules that allows us to accomplish receiver attempt greater than one thousand occasions quicker. Then an under-sampling established transmitter try out scheme is gifted. The scheme can effectively extract the transmitter jitter and end the complete transmitter try inside 100ms, whereas the try often takes seconds. The booklet additionally provides and exterior loopback-based trying out scheme, the place and FPGA-based BER tester and a unique jitter injection strategy are proposed. those schemes may be utilized to validate, try out and debug HSSIs with information expense as much as 12.5Gbps at a decrease try out fee than natural ATE recommendations. furthermore, the publication introduces an efficieng scheme to enforce excessive functionality Gaussian noise turbines, appropriate for comparing BER functionality below noise conditions.
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Additional resources for Accelerating Test, Validation and Debug of High Speed Serial Interfaces
Similar to the transmitter BER scan, we perform a receiver BER scan. We collect data points at higher BER levels, which takes much less time to do. Then we extrapolate performance to the lower BER range. The extrapolation accuracy can be easily verified by performing the test at the lower BER range, and comparing it to the extrapolation result. If the error is small, then the new method is considered acceptable. However, there are two significant differences between the receiver BER scan and the transmitter BER scan.
Without amplitude noise, the receiver can always correctly recover the transmitted bit. Under the presence of jitter and noise, the transition edge of the signal can fluctuate horizontally across the sampling point (along the time axis), and the signal voltage can fluctuate vertically at the sampling point (along the voltage axis). Both the time deviation and amplitude deviation can cause a bit error – bit “0” is received as bit “1” or bit “1” is received as bit “0”. 2 Timing Jitter 21 If we ignore the setup time and hold time requirements , timing jitter can cause bit errors in the following two conditions: • For logic “1”, the rising edge lags behind the sampling instance or the falling edge is ahead of the sampling instance • For logic “0”, the falling edge lags behind the sampling instance or the rising edge is ahead of the sampling instance Amplitude noise causes bit errors in the following two situations: • For logic “1”, the voltage level at the sampling instance is smaller than the threshold voltage • For logic “0”, the voltage level at the sampling instance is bigger than the threshold voltage The timing and amplitude noise impacts on BER can be characterized by two parameters – Jitter and Signal-to-Noise Ratio (SNR).
We refer the readers to references such as  for more details on the noise sources affecting the PLL operation. Figure 3-3 shows the frequency behavior of the PLL . The function φout(f)/ φin(f) is the input jitter transfer function, showing a low-pass characteristic. Therefore, the PLL tracks the jitter in the input signal with jitter frequencies below the PLL bandwidth fPLL (in-band jitter). The function φout(f)/ φnoise(f) is the VCO jitter transfer function, showing a high-pass characteristic.